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Design & Simulation 001
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M(ixed)I(nterconnets)Package
M(ixed)I(nterconnets)Package
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Cerimic/Metal Package
Cerimic/Metal Package
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CSP（Chip Scale Package）
CSP（Chip Scale Package）
BGA/LGA/PGA
BGA/LGA/PGA
BGA/LGA/PGA

TO Packages

TO package, originally referring to Transistor Outline Package, is a packaging technology for transistors designed to allow leads to be formed and used for surface mounting. For example, in TO-220-5, TO-220 represents the type of packaging, and the subsequent 5 indicates the number of its pins
TO252,WanYing Chip Packaging & Testing Electronics Co., Ltd.,TO252

TOLL-8
TO247-4L,WanYing Chip Packaging & Testing Electronics Co., Ltd.,TO247-4L

TO263-7L
TO247-3L,WanYing Chip Packaging & Testing Electronics Co., Ltd.,TO247-3L

TO252-4L
TO220-5L,WanYing Chip Packaging & Testing Electronics Co., Ltd.,TO220-5L

TO247-4L
TO220-3L,WanYing Chip Packaging & Testing Electronics Co., Ltd.,TO220-3L

TO247-3L
EPLQFP20X20-144L,WanYing Chip Packaging & Testing Electronics Co., Ltd.,EPLQFP20X20-144L

TO220-5L
MSOP10L,WanYing Chip Packaging & Testing Electronics Co., Ltd.,MSOP10L

TO220-3L
FEATURED
Design & Simulation
Design & Simulation
Design & Simulation 001
WB (Wire Bond)
WB (Wire Bond)
WB (Wire Bond)
FC (Flip Chip)
FC (Flip Chip)
FC (Flip Chip)
M(ixed)I(nterconnets)Package
M(ixed)I(nterconnets)Package
M(ixed)I(nterconnets)Package
2.5/3D Package
2.5/3D Package
2.5/3D Package
Cerimic/Metal Package
Cerimic/Metal Package
Cerimic/Metal Package
CSP（Chip Scale Package）
CSP（Chip Scale Package）
CSP（Chip Scale Package）
BGA/LGA/PGA
BGA/LGA/PGA
BGA/LGA/PGA

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Telephone: 028-60239629
Telephone: 028-60239629
Email: service@wanyingtek.com
Email: service@wanyingtek.com
Address: No. 203, Shuangbai East 1st Street, High-Tech Zone, Chengdu, Sichuan Province, China
Address: No. 203, Shuangbai East 1st Street, High-Tech Zone, Chengdu, Sichuan Province, China
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