The Cerimic/Metal Package is a hermetic cavity package: a metal, ceramic and glass body with an internal cavity sealed under high-purity nitrogen or another inert gas. The die sits inside that controlled atmosphere instead of under a mould compound, which is the single design decision separating this part from the plastic and organic substrate formats elsewhere in our range. It is specified for integrated circuits and discrete components that have to keep working for years in conditions where a moulded body gradually loses its margin.
Aerospace and defense electronics are the heart of this work, and the same construction carries into medical electronics, automotive sensor modules and communications hardware where a field failure is not an acceptable outcome.
The part is built inside our advanced semiconductor packaging work, so cavity geometry, the lid seal and the inspection routine are designed around your die rather than picked from a stock list. If your program is still weighing a moulded body against a sealed cavity, bring the operating conditions to the engineering review and the trade-off gets worked through on paper before anything is built.
| Package type | Hermetic cavity package, non-moulded |
| Body materials | Metal, ceramic and glass |
| Cavity atmosphere | High-purity nitrogen or another inert gas |
| Sealing | Hermetically sealed internal cavity |
| Device types | Integrated circuits and discrete components |
| Typical sectors | Aerospace, defense, medical electronics, automotive, communications, AI hardware |
| Quality controls | Design control, precision testing and inspection |
| Custom outlines | Built to your die, pinout and board footprint |
| Build documentation | Compliance and certificate documents for the build |
Everything about this package is decided by one requirement: the die has to stay dry. The envelope is assembled from a metal body, ceramic sections and glass seals, and the glass carries the most risk. It has to wet both the metal and the ceramic and cool into a continuous, leak-tight boundary. Get that joint right and the cavity holds; get it wrong and the part never leaves the building.
Before the lid goes on, the cavity is purged and backfilled with high-purity nitrogen or another inert gas. Oxygen and water vapour are displaced, so what remains inside is a dry, non-reactive atmosphere rather than air. That is the difference that matters over a long service life: water vapour and airborne particles are the two failure drivers that quietly push high-reliability microelectronics out of specification, and a sealed cavity removes both rather than slowing them down.
The internal volume is kept close to the die rather than generously oversized, so there is less residual gas to stabilise after sealing and less volume that can shift with temperature. Finished parts come out as a flat body with a gold-plated lid and a pin array around the base, a shape most assembly lines already know how to handle.
Sealing, backfill and inspection sit inside one advanced semiconductor packaging workflow rather than being split across three subcontracts, so a cavity problem is caught where it happens.
Package selection is rarely a catalogue decision. Our engineers review your die, interconnect and thermal requirements together with your design team before anything is built, and recommend the package format and lead count that suit your board, your test plan and your production volume. Because design simulation, manufacturing and reliability testing sit within the same team, feasibility questions and qualification findings come back with a clear answer. Drawing on more than 30 years of shared packaging expertise, we also help trace yield and reliability problems back to their root cause.
Metal, ceramic and glass, working as one envelope. The metal body carries mechanical strength and heat, the ceramic insulates the conductors and holds the cavity dimensions, and the glass seals the two together so there is no polymer joint anywhere in the boundary. The cavity itself is backfilled with high-purity nitrogen or another inert gas before the lid is closed, which is the second half of the answer — a good seal around ordinary air would still leave oxygen and water vapour inside with the die. Both halves are designed together as part of the advanced semiconductor packaging route for the part.
Custom is the standard route. Cavity size, pinout, lid style and seal configuration are set from your die and board drawing, and feasibility is reviewed before any tooling is committed. Send design files or an RFQ and the engineering team comes back with a proposed package plus the points that actually decide it — thermal path, pin count, test access. As a chip packaging service provider we would rather tell you early that a different format suits the application than build something that has to be redesigned.
The regime is deliberately conservative: design control before the build, a qualified process window during it, precision testing of the sealed cavity afterwards, and inspection before packing. Failures are traced to the process step that caused them rather than explained away, because a marginal seal that passes at the end of the line can still surface years later. For programs where the device cannot fail, that discipline matters more than the headline specification — and it is the part of the program semiconductor packaging companies are judged on once a design reaches volume.
Aerospace, biomedical and automotive electronics are the three that lean on it hardest, because each of them measures reliability over a service life rather than at a test bench. Integrated circuits and discrete components that cannot tolerate moisture or particulate ingress are the natural fit, along with communications modules and compute hardware that have to hold their electrical behaviour under load for years. Where the environment is the dominant risk, it is why teams look to semiconductor packaging companies that can seal a cavity rather than mould a body.
Yes, when the system calls for it. Chiplet packaging and other multi-die builds can be housed in a single sealed cavity so several components share one protected, inert atmosphere instead of being moulded separately. The limit is set by cavity geometry, thermal load and the pinout you need rather than by a fixed outline, so bring the die stack and the power map to the engineering review and the cavity is sized around them.
Outlines follow your die and board footprint rather than a catalogue. Cavity height, wall thickness, pin count and lid style are agreed during package definition, then checked by simulation before tooling. Because a hermetic part cannot be adjusted after sealing, the drawing is reviewed and signed off first — the advanced packaging team will flag any feature that would compromise the seal. Send your board drawing with the RFQ and we come back with a proposed outline.
