Microsystem Integration Overview
A digital system-in-package starts from an integration problem, not from a package drawing. Several different die — logic, memory, an accelerator — have to sit close enough together to behave as one microsystem, inside a footprint that keeps shrinking. D-SiP answers that with heterogeneous integration: 2.5D and 3D build-up brings accelerators, processors and memory die together in a single SiP system in package rather than spreading them across a board.
The work suits teams that already know what their die set has to do: fabless design houses finishing a multi-die product, system houses building modules around third-party silicon, and R&D groups that need parts from different sources to share one substrate. You keep the die and the architecture; the package, the interconnect, the assembly and the test programme are our side of the work.
A module like this usually replaces a board-level cluster of separate packages or an older wire-bond multi-chip assembly. What the product gets back is board area, shorter links between die, one component to qualify instead of several, and a shorter path from a working prototype to a production module.
Every SiP package is built to a program. There is no stock part number to order from a shelf — the die arrangement, the substrate, the build sequence and the test plan are settled with your team before anything is tooled.
Package Architecture
| Package family | Digital SiP for heterogeneous die integration |
| Integration platform | 2.5D/3D packaging and system-in-package build-up |
| Heterogeneous die | Digital logic, memory and accelerator die in one package |
| Architecture style | Chiplet-based partitioning of digital logic |
| Interconnect | Dense die-to-die and die-to-substrate links inside the package |
| Front-end work | Solution development, design simulation, DFM validation |
| Manufacturing | In-house advanced packaging with stage-by-stage process control |
| Back-end work | Test, reliability assessment, failure analysis |
| Program scope | Prototype builds through to volume production |
| Typical fit | High-performance computing, AI acceleration, embedded systems |
Use Scenarios
- AI acceleration modules in high-performance computing: CPUs, GPUs and NPUs consolidated into one SiP system in package so working data moves inside the package instead of across a board. Teams building for data centers and dense compute enclosures use this to hold latency while keeping the module compact enough to fit.
- Edge AI devices: where the enclosure has little airflow and no room for a second package, memory and logic die are combined in a chiplet architecture so the device still carries the compute its application needs.
- Industrial embedded control: memory, logic and an FPGA combined through heterogeneous integration into a compact, rugged microsystem for automated manufacturing equipment, built to keep working through vibration and harsh plant environments.
- Automotive electronics: multi-die modules for vehicle systems, where several functions have to share one compact package and the evidence behind the build has to come from the same chain that made the parts.
- Communications equipment: digital processing and memory for infrastructure boards, integrated so the area around the line-side circuitry stays free.
- Prototype-to-volume programs: teams that start with a handful of modules for bench validation and need the same package, the same process and the same test limits when the product ramps.
Design Simulation and DFM
- Send the die set and the target: the die you want integrated, the outline you are aiming for or the space you have, the board the module will sit on, and the electrical and thermal targets the product has to meet.
- Partition the design: we work out how the die should be arranged and interconnected using 2.5D/3D packaging, where the critical die-to-die links run, and how the chiplet split should fall. This is the step that decides how much of the design is still inexpensive to change.
- Simulate before tooling: thermal and electrical simulation of the proposed SiP package covers the heat path, interconnect parasitics, signal integrity and power delivery. Findings are reviewed with your engineers while the design is still open.
- Validate for manufacturing: the chiplet architecture is checked against the substrate and assembly rules our line actually runs, so a design that simulates well can also be built repeatably.
- Agree the build documentation: the final stack, the process flow and the inspection points become the build package both sides work from.
- Carry the model into test: simulated behavior sets the expectations the test programme and any later failure analysis are measured against.
Electrical and Thermal Behavior
Most of the electrical gain in a heterogeneous integration module comes from distance. Links that would otherwise run across a board become short die-to-die connections inside the package, which lowers interconnect parasitics and leaves signal integrity work far less to fight. The interconnect is designed with those links in mind, so a high-speed interface between two die is treated as part of the package from the start rather than as a routing problem handed to your board team.
Power delivery in 2.5D/3D packaging is planned on the same terms. Several die switching at once draw current through one package, so the delivery network is designed together with the stack instead of being added at the end. On the thermal side, the heat path is decided when die are placed: a device that runs hot gets a position and a route to the package exterior that can carry its heat, and the design assumes sustained load rather than a favorable-case burst.
Because the arrangement is simulated before it is built, electrical and thermal behavior can be reviewed with your engineers while changes are still inexpensive. Bring the operating envelope, the power budget and the thermal limits the product has to hold — those three inputs shape the package more than any other part of the brief.
Manufacturing, Test and Failure Analysis
- In-house build: assembly runs on our own advanced packaging line, so the process that was simulated is the process that runs.
- Stage-by-stage control: every step has a check before the module moves on, which keeps a deviation at the stage where it happened instead of at final test.
- Test programme agreed up front: which parameters are measured, at which stage, and what counts as a pass are settled with your team before the first build.
- Reliability assessment after build: modules go through reliability work before release, and the results go into the documentation your qualification file needs.
- Failure analysis with a route back to design: when a module fails, the build record is used to trace the cause to design, material or process, and the finding re-enters the design loop rather than being logged and closed.
- Reproducibility across lots: the same documented flow, the same inspection points and the same test limits apply to every build.
- One partner through the chain: working with a single chip packaging service provider from simulation to failure analysis means the die are not handed between vendors between stages, and nobody has to reconstruct what the previous house did.
Project Assessment and Ordering
- Send the die set and the application: a list of the die with their function, the outline you have in mind or the space available, the target board, and the electrical and thermal targets. An existing package drawing or a previous module is a useful starting point if you have one.
- Say where the program stands: first silicon, a redesign of an existing module, and a ramp all need a different first review, and it changes what we ask for. If the die set is sensitive, an NDA can be put in place before files are exchanged.
- Get an engineering response: an engineer reviews the design files and the application, and we reply within 24 hours of receiving your files or RFQ.
- Review the assessment: you get a proposed integration approach, the questions that still need answering, and a view of where the risk sits in the stack — before a quotation is built on assumptions.
- Quotation and build plan: as an advanced packaging manufacturer we quote from the agreed build package, with prototype and volume quantities set out separately. Lead time and commercial terms are confirmed with your sales contact at this point.
- Delivery and export: shipment runs through our one-stop export service, with the export documentation your import process needs handled as part of the order.
- Stay on the program: as a chip packaging service provider across design, build and analysis, the same team follows the module from first samples through to volume, so nothing has to be learned again at ramp.
Heterogeneous Die Compatibility
- Die from different foundries and process nodes is the normal case, not the exception. An advanced-node accelerator, a memory die from a memory maker and a mature-node controller rarely come from one source, and a chiplet architecture lets each die stay where it is instead of waiting for everything to move to the same node. What has to be settled is how they meet inside the package, not whether they can.
- Die-to-die links are matched to the interface each die actually presents. Where two die already speak the same parallel or serial protocol they can be coupled directly; where the protocols differ, an interposer layer or a bridge die carries the connection. That call is made during partitioning, before the substrate is tooled, because it changes the routing density the stack has to carry.
- Pad pitch and die thickness vary with node, and the assembly plan absorbs the difference. A die on a mature node usually arrives thicker with wider pads than the advanced-node die sitting next to it, so heights are leveled at the substrate and the interconnect is planned per die rather than to one blanket specification.
- Every die is treated as known-good before it enters the stack. Placing an untested die beside an expensive advanced-node device risks scrapping both, so the test coverage applied to each source is agreed with your team first and runs before assembly.
- Supply rails are mapped die by die. Mixed-source silicon seldom shares the same voltage domains or the same noise tolerance, so the power delivery plan keeps domains separate where they need to be and defines where they can be joined.
- Heat is planned from the power each die actually dissipates. Density varies widely between a logic die, a memory stack and an I/O die, so the thermal map is built from the per-die power figures you give us and placement follows it — a hot die gets a short path out of the package rather than a position chosen for layout convenience.
- Some combinations need a conversation before we commit. If a die offers only a proprietary interface that cannot be bridged, if its pads cannot be re-routed, or if a licence restricts how it is re-timed inside a module, that constraint fixes the arrangement and we will say so at assessment rather than after tooling.
- Third-party and purchased die are handled exactly like your own silicon: interface documentation, pad layout and test access are the three things we ask for, with an NDA in place wherever the source requires one. Send the die list with each interface and its power figures, and the review will separate what is routine from what needs engineering.
Technical Support & Model Matching
Package selection is rarely a catalogue decision. Our engineers review your die, interconnect and thermal requirements together with your design team before anything is built, and recommend the package format and lead count that suit your board, your test plan and your production volume. Because design simulation, manufacturing and reliability testing sit within the same team, feasibility questions and qualification findings come back with a clear answer. Drawing on more than 30 years of shared packaging expertise, we also help trace yield and reliability problems back to their root cause.
FAQ
Which chip types can be integrated in one D-SiP?
AI accelerators, CPUs, GPUs, NPUs, memory and FPGAs, in whatever mix the product needs. What has to be workable is the combination — power domains, die-to-die interfaces and heat — so send the die list with your enquiry and we will say plainly which mixes are practical inside a single SiP package.
Can the package be designed around our own requirements?
That is how every one of these packages is built. There is no fixed outline to choose from: the arrangement, the stack, the interconnect and the test plan are developed around your die set, your board and your application targets. Simulation and DFM validation run before the build package is fixed, so the SiP system in package you approve has already been checked for manufacture.
How do 2.5D and 3D build-up differ in practice?
2.5D places the die side by side on an interposing layer and connects them laterally; 3D stacks die vertically. 2.5D usually gives the flatter, easier-to-cool arrangement, while 3D shortens the vertical links and saves more area at the cost of concentrating heat in a smaller volume. Where the choice is close we simulate both and recommend the one your thermal and electrical targets can hold — the sort of call a semiconductor packaging manufacturer should make with your engineers rather than for them.
Can die from different foundries or process nodes sit in one package?
Yes, and that is usually the reason the program exists. Chiplet-style partitioning lets logic from one source, memory from another and third-party IP share a module without waiting for everything to move to the same node. The die-to-die interface, the power domains and the thermal map have to be settled together, which is easier when a single chip packaging service provider owns the whole module rather than one stage of it.
How does the module change what our board team has to do?
The module arrives as one component, so the board carries a single part where several used to sit, and the links between the integrated die never appear on your PCB. Layout usually simplifies and there are fewer parts to qualify. Your board team keeps the interface at the package boundary — pin-out, power and the connection into the rest of the system — and that is the part worth reviewing with us before the build package is signed off.
