A substrate package carries one or more dies on an organic substrate — FR-4 or BT resin — or on a ceramic carrier, in place of the metal leadframe used in moulded parts. Connections leave the die by wire bonding or by flip-chip bonding, and build-up layers inside the carrier fan them out to a ball or land array underneath. The carrier does the routing, so the package is planned around the die and the board rather than around a fixed outline.
Design teams move to this format when a leadframe part runs out of routing room, when a multi-die architecture has to fit a board area that cannot grow, or when the die-to-board connection itself starts limiting the signal. Most of our SiP system in package work sits in communications, high-performance computing and mobile products, where several functions share one footprint.
As a chip packaging service provider we build the carriers in-house, run wire bonding and flip-chip on the same line, and keep design simulation, manufacturing, test and failure analysis with one engineering team. When a stack-up question or a warpage finding appears mid-programme, the answer comes from the engineers who will build the part.
| Property | Specification |
|---|---|
| Organic substrate | FR-4 or BT resin |
| Ceramic substrate | Ceramic carrier for builds that need greater thermal and mechanical stability |
| Routing | Build-up process layers, set by the substrate design rules |
| Interconnect methods | Wire bonding, flip-chip, or both in one package |
| Die integration | Single die or multi-die |
| Package formats | BGA, CSP and flip-chip |
| Standard substrate size | 240 mm × 70 mm |
The high pin density a SiP package can reach is set by the substrate design rules — line width, line spacing and the number of layers in the build-up process — more than by the body size alone. Two designs with the same outline can land on very different connection counts depending on how the stack-up is planned, which is why the substrate layout is worked out alongside the pad ring rather than after it.
On a dense SiP semiconductor design the pad ring usually decides the escape pattern. A wire-bonded die needs pad positions that clear the wire loop, so the fan-out is planned around loop height and pad pitch. A flip-chip die places bumps across the die face, which spreads connections over the whole die area and takes pressure off the perimeter.
The board side matters as much as the die side. The ball pitch you can use, the routing layers available on the PCB and the power and ground return paths all shape what the substrate has to deliver, and on large, thin carriers the stack-up has to stay balanced or the package will bow during assembly. Die drawing, pad ring and board layout are reviewed together, so the substrate design rules are fixed against all three at once before the layout is released.
| Step | Detail |
| To open a review | Die layout, pad ring, package outline, pin count, thermal and electrical targets |
| First reply | Within 24 hours of your RFQ |
| Stages covered | Prototype builds through high-volume manufacturing |
| Quotation and lead time | Confirmed for your project once the review is complete |
| Export handling | One-stop export service |
| Design changes | Agreed with our engineers before the build starts |
| Documentation | Inspection and compliance records supplied with the project |
Package selection is rarely a catalogue decision. Our engineers review your die, interconnect and thermal requirements together with your design team before anything is built, and recommend the package format and lead count that suit your board, your test plan and your production volume. Because design simulation, manufacturing and reliability testing sit within the same team, feasibility questions and qualification findings come back with a clear answer. Drawing on more than 30 years of shared packaging expertise, we also help trace yield and reliability problems back to their root cause.
We work with an organic substrate such as FR-4 or BT resin, and with a ceramic substrate where the application needs more thermal and mechanical stability. The choice interacts with the rest of the design: it sets the achievable line width and layer count, and it governs how flat the carrier stays through assembly, so material, stack-up and interconnect are fixed together rather than one at a time.
Yes. As a semiconductor packaging manufacturer we set the substrate material, layer count, interconnect method — wire bonding, flip-chip or both — and the package format from your die and your board rather than from a fixed catalogue outline. The review starts from the die drawing, the pad ring and the board layout, and comes back as a proposed stack-up with any limits on pin count, thermal performance or body size called out.
We do. Both interconnect methods run on the same platform, and one package can mix them — a proven wire-bonded die next to a flip-chip die that needs the shorter connection. That mix is often what makes a multi-die SiP package practical, because each die gets the interconnect its performance needs instead of the one the format happens to allow.
Communications equipment, high-performance computing, mobile and wearable terminals, automotive and industrial control modules, medical and instrumentation electronics, plus system-in-package development in research groups. As a chip packaging service provider we keep the same engineering and inspection process across all of them, so a first prototype for a research group is built the way a production order is built.
Usually at the point where the leadframe runs out of room — the pin count no longer fits the outline, the thermal path through the frame is too long, or a second die has to join the first. A substrate adds build-up layers and much higher pin density in the same body size, in exchange for a substrate design review before tooling is released.
Heat leaves the die through the bumps into the substrate and then into the board, a much shorter route than a wire-bonded part offers. The thermal behaviour is modelled before the build, so the copper in the substrate and the copper in the board are planned as one path; where the budget is tight, the stack-up and the board layout are adjusted together rather than one after the other.
Stack-up balance is the main lever: the thickness and copper distribution on either side of the carrier are set so the package stays flat through reflow and test. Where a design is unusually large or thin, that balance is confirmed before tooling rather than corrected after the first build.
